1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor chips and methods of shaping the same.
2. Description of the Related Art
Flip-chip techniques are frequently used to mount a semiconductor chip or die to a substrate of one sort or another, such as a package substrate or other type of circuit board. In a typical conventional process, a semiconductor chip is singulated from a wafer as a rectangular structure that has four orthogonal corners. Thereafter plural solder joints are formed between the chip and the substrate by selective solder bump deposition on both the chip and the substrate followed by a reflow to merge the sets of bumps. An underfill material is next placed between the mating surfaces of the semiconductor chip and the substrate. Semiconductor, substrate and solder joint materials typically have quite different coefficients of thermal expansion (CTE) and thus different thermal strain rates. The underfill material is designed to lessen the effects of the sometimes wide differences in CTE.
Solder joint fatigue is one of the key reliability issues related to flip-chip assembly on organic substrates. Solder joint fatigue is a function of several factors including: (1) large coefficient of CTE mismatch between a silicon die and the package substrate; (2) die size; (3) various geometrical factors related to the solder bumps, such as shape, size and height; (4) underfill and substrate material properties; and (5) the types of thermal cycling the joints must endure.
Die size is closely related to solder joint stress. The stresses on solder joints increase from a small value at the die center or neutral point to some higher value near the edges of the die. However, the outermost solder joints, those that are most distant from the die center or neutral point, are subjected to the maximum stresses. The stresses are highest for those joints located at the die corners.
One potential problem associated with high stresses at a die perimeter is the potential for the delamination of an underfill material layer from the die, particularly at the orthogonal corners. If the delamination occurs in critical areas or is sufficiently widespread, various unwanted mechanical effects may follow such as chip cracking, solder joint fatigue failure and so on.
One conventional technique for addressing the edge effect involves the use of sacrificial dummy bumps. As the name implies, dummy bumps are not connected to chip circuitry, but are instead set aside for reinforcement. Dummy bumps do help. But because they occupy sites that could otherwise be used for input/output, routing is constrained. If routing is to be maintained, then the die size must be increased with an attendant penalty in terms of material and processing cost.
Another conventional technique involves experimenting with underfill chemical compositions to try to prevent delamination. Chemical solutions to such problems may not be readily available.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.